SRAMs may be structured so that two or more SRAM cells are connected in parallel to one or more write bit lines. The write bit line(s) are coupled to a data input through a write driver logic. Prior to a write operation, the write driver logic may drive one of the write bit lines high, in conjunction with driving another of the write bit lines low, in response to a logic value applied to the data input. A particular SRAM cell is selected for writing by activating the cell's write word line. Once an SRAM cell's write word line is activated, the data value represented by the logic state(s) of the write bit line(s) may be written into the SRAM cell. The write word line is deactivated following the write operation. The state of the write bit line(s) may be changed prior to the next write operation.
FIG. 1 is a schematic representation of a portion of a prior art SRAM circuit 100 having a column of SRAM cells 110, a write driver logic 156, a data input (DATA) 150, a write bit line (WBL) 160, and a write bit line complement (WBLC) 158. Each cell 110 includes a pair of cross-coupled inverters, 130, 132, a write word line (WWL) 108, a read word line (RWL) 106, and a read data line (RD) 103. Each cell 110 also includes NFET pass transistors 1N1 and 1N2, read transistors 1N3 and 1N8, and the nodes data true (TRU) 104 and data complement (CMP) 102.
SRAM cells 110 are coupled to the write driver logic 156 through the WBL 160, and the WBLC 158. The transistors depicted in FIGS. 1, 2 and 4 will be recognized by one with ordinary skill in the art to be arranged to implement functions including pass gates, pull-up and pull-down devices.
The write driver logic 156 is comprised of inverter 162 coupled to DATA 150 and WBLC 158, and inverter 164 coupled to WBLC 158 and WBL 160. Inverters 162 and 164 are connected so as to invert and buffer (respectively) the logic value of DATA 150, while driving WBLC 158 and WBL 160, respectively with complimentary logic values. While the write bit line in this prior art example comprises two complimentary write bit lines WBL 160 and WBLC 158, other types of SRAMs are contemplated which may employ only a single write bit line.
WBL 160 and WBLC 158 are connected to all SRAM cells 110 in a particular SRAM cell column, and distribute the logic value present on DATA 150 to all SRAM cells 110 within that column. Transistors 1N1 and 1N2 and WWL 108 are used to control the write operation to SRAM cell 110. Each SRAM cell 110 of an SRAM column has its own WWL 108, RWL 106, and RD 103, but only one of each is shown for simplicity of the text and figures.
One of ordinary skill in the art will recognize that “0” and “1” refer to logical “zero” and “one” values, respectively.
A write operation employs the write driver logic 156. As an illustration, to write a 1 to the cell 110, a 1 data value is applied to the DATA 150 input. The write driver logic 156 inverts and buffers the 1 value using inverters 162 and 164, driving a 1 on WBL 160 and a 0 on WBLC 158. WWL 108 is subsequently used to turn on pass transistors 1N1 and 1N2, applying the 1 present on the WBL 160 and the 0 present on the WBLC 158 to the cross-coupled inverters 130 and 132 within SRAM cell 110. The 1 data value applied to DATA 150 is then written into the SRAM cell 110. After the data write operation, the WWL 108 is disabled, shutting off pass transistors 1N1 and 1N2. The logic value on the DATA 150 may then change in preparation for a further write operation
A read operation employs the transistors 1N3 and 1N8 and the RWL 106 to enable reading, and RD 103 as an output capable of indicating the data read from SRAM cell 110. Each SRAM cell 110 includes transistors 1N3 and 1N8, an RWL 106 and an RD 103, although these are only shown in one cell 110 (FIG. 1) for simplicity of figures and descriptions.